VHDL GHDL

Logic gate for an 8-bit Conditional Sum Adder ( CSA8 ). Here carry_in ( C_in ) and carry_out ( C_out ) are used (in the eventuality of a 16-...

Logic gate for a 10 to 5 Multiplexer (10to5MUX): It has three inputs: 1-bit sel (selector), 5-bit X[4..0] and 5-bit Y[4..0] . It uses a...

Logic gate for an 8 to 4 Multiplexer (8to4MUX): It has 3 inputs: 1-bit sel (selector), 4-bit X[3..0] and 4-bit Y[3..0] . It uses two 4t...

Logic gate for a 4 bit Conditional Sum Adder (CSA4): It uses three inputs:  one 1-bit C_in (carry in) and two 4-bit summands X[3..0] , Y...

Logic gate for a 6 to 3 Multiplexer: It uses three inputs: one 1-bit sel (selector), 3-bit X (X0, X1, X2) and 3-bit Y (Y0, Y1, Y2), it...