6 to 3 Multiplexer

Logic gate for a 6 to 3 Multiplexer:

It uses three inputs: one 1-bit sel (selector), 3-bit X (X0, X1, X2) and 3-bit Y (Y0, Y1, Y2), it also uses a 4to2 multiplexer (MUX4_2), two AND gates and one OR gate. It has a 3-bit output m.

VHDL code for the 6 to 3 Multiplexer:

-- 6 to 3 Multiplexer
-- inputs: 1bit sel, 3bit X, 3bitY
-- outputs: 3bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity MUX6_3 is
    PORT( sel: IN bit; 

          X, Y: IN bit_vector(2 downto 0);
          m: OUT bit_vector(2 downto 0));
end MUX6_3;


architecture logic of MUX6_3 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
              m0 => m(0), m1 => m(1));
             
    m(2) <= (X(2) and sel) or (Y(2) and not sel);
end logic;