4 to 2 Multiplexer

Logic gate for a 4to2 Multiplexer:

It uses five inputs: 2-bit X, 2-bit Y and 1-bit sel (selector), two 1 bit outputs: m0 and m1, four AND gates, two OR gates and a NOT gate.

VHDL code for the 4to2 Multiplexer:

-- 4to2 Multiplexer

-- inputs: sel, X0, X1, Y0, Y1

-- outputs: m0, m1

LIBRARY ieee;

USE ieee.std_logic_1164.all; 

entity MUX4_2 is

   PORT( sel: in bit; X0: in bit; X1: in bit; Y0: in bit; Y1: in bit;

         m0: out bit; m1: out bit); 

end MUX4_2; 

architecture logic of MUX4_2 is
begin 

   m0 <= (X0 and sel) or (Y0 and not sel);
   m1 <= (X1 and sel) or (Y1 and not sel);
end logic;