1-bit Full Adder

Logic gate for an 1-bit Full Adder:

It uses three 1-bit inputs: C_in (carry in), X, Y, two 1-bit outputs: S and C_out (carry out), two half adder (HA) blocks and one OR gate.

The VHDL code for the 1-bit Full Adder:

-- 1 bit Full Adder
-- inputs:  C_in, X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity FA is
    PORT( C_in : IN bit; X: IN bit; Y: IN bit;
          S: OUT bit; C_out: OUT bit);
end FA;

architecture logic of FA is

    component ha is
        PORT( X: IN bit; Y: IN bit;
              S: OUT bit; C_out: OUT bit);
    end component;
   
    signal ha2Y: bit;
    signal or2Y: bit;
    signal or2X: bit;
           
begin
    ha_inst0: HA
    PORT MAP(
        X => X, Y => Y,
        S => ha2Y, C_out => or2Y);
       
    ha_inst1: HA
    PORT MAP(
        X => C_in, Y => ha2Y,
        S => S, C_out => or2X);
       
    C_out <= or2X OR or2Y;
   
end logic;