1-bit Half Adder

Here is the logic gate for an 1-bit Half Adder (HA)

It uses two 1-bit inputs: X and Y, two 1-bit outputs: S and C_out (carry out), one XOR gate and one AND gate.

And here is the VHDL equivalent code:

-- 1 bit Half Adder
-- inputs: X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity HA is
   PORT( X: in bit; Y: in bit;
         S: out bit; C_out: out bit);
end HA;

architecture logic of HA is 
begin
    S <= X xor Y;
    C_out <= X and Y;
end logic;