8-bit Conditional Sum Adder (CSA8)

Logic gate for an 8-bit Conditional Sum Adder (CSA8). Here carry_in (C_in) and carry_out (C_out) are used (in the eventuality of a 16-bit extension).

It has three inputs: 1-bit C_in (carry_in - not used in the VHDL code!), 8-bit X[7..0] and 8-bit Y[7..0]. It uses three 4-bit Conditional Sum Adder (CSA4) blocks and one 10 to 5 Multiplexer (10to5MUX) block. It has two outputs: 8-bit S[7..0] and C_out (carry_out - not used in the VHDL code!).

VHDL code for the 8-bit Conditional Sum Adder (CSA8):

-- 8-bit Conditional Sum Adder (CSA8)
-- inputs: X[7..0], Y[7..0]
-- outputs: S[7..0]
-- carry_in and carry_out not used!!! (do not intend to extend on 16-bit!)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity CSA8 is
    PORT (X, Y: in bit_vector(7 downto 0);
          S: out bit_vector(7 downto 0));
end CSA8;

architecture logic of CSA8 is

    component CSA4 is
        PORT( C_in: in bit;
              X, Y: in bit_vector(3 downto 0);
              S: out bit_vector(3 downto 0);
              C_out: out bit);
    end component;
   
    component MUX10_5 is
        PORT( sel: in bit;
              X, Y: in bit_vector(4 downto 0);
              m: out bit_vector(4 downto 0));
    end component;
   
    constant c: bit := '1';
    signal msel: bit;
    signal mx, my: bit_vector(4 downto 0);
   
   
begin
    csa4_inst0 : CSA4
    PORT MAP( C_in => '0', X => X(3 downto 0), Y => Y(3 downto 0),
              S => S(3 downto 0), C_out => msel);
             
    csa4_inst1 : CSA4
    PORT MAP( C_in => c, X => X(7 downto 4), Y => Y(7 downto 4),
              S => mx(3 downto 0), C_out => mx(4));
             
    csa4_inst2 : CSA4
    PORT MAP( C_in => not c, X => X(7 downto 4), Y => Y(7 downto 4),
              S => my(3 downto 0), C_out => my(4));
             
    mux10_5_inst0 : MUX10_5
    PORT MAP( sel => msel, X => mx, Y => my,
              m(3 downto 0) => S(7 downto 4));         
end logic;

10 to 5 Multiplexer

Logic gate for a 10 to 5 Multiplexer (10to5MUX):

It has three inputs: 1-bit sel (selector), 5-bit X[4..0] and 5-bit Y[4..0]. It uses a 6 to 3 Multiplexer block (6to3MUX) and a 4 to 2 Multiplexer block (4to2MUX). It has a 5-bit output m[4..0].

VHDL code for the 10 to 5 Multiplexer:

-- 10 to 5 Multiplexer
-- inputs: 1-bit sel (selector), 5-bit X, 5-bit Y
-- outputs: 5-bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity MUX10_5 is
    PORT( sel: in bit;
          X, Y: in bit_vector(4 downto 0);
          m: out bit_vector(4 downto 0));
end MUX10_5;

architecture logic of MUX10_5 is

    component MUX6_3 is
        PORT( sel: in bit;
              X, Y: in bit_vector(2 downto 0);
              m: out bit_vector(2 downto 0));
    end component;
   
    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin

    mux6_3_inst0 : MUX6_3
    PORT MAP( sel => sel, X => X(2 downto 0), Y => Y(2 downto 0),
              m => m(2 downto 0));
             
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(3), X1 => X(4), Y0 => Y(3), Y1 => Y(4),
              m0 => m(3), m1 => m(4));
             
end logic;

8 to 4 Multiplexer

Logic gate for an 8 to 4 Multiplexer (8to4MUX):

It has 3 inputs: 1-bit sel (selector), 4-bit X[3..0] and 4-bit Y[3..0]. It uses two 4to2 Multiplexer blocks (4to2MUX). It has one 4-bit output m[3..0].

VHDL code for the 8to4 Multiplexer:

-- 8 to 4 Multiplexer
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity MUX8_4 is
    PORT( sel: in bit;
          X, Y: in bit_vector(3 downto 0);
          m: out bit_vector(3 downto 0));
end MUX8_4;


architecture logic of MUX8_4 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
              m0 => m(0), m1 => m(1));
             
    mux4_2_inst1 : MUX4_2
    PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
              m0 => m(2), m1 => m(3));        
end logic;

4-bit Conditional Sum Adder (CSA4)

Logic gate for a 4 bit Conditional Sum Adder (CSA4):

It uses three inputs:  one 1-bit C_in (carry in) and two 4-bit summands X[3..0], Y[3..0]. It makes use of three 2-bit Conditional Sum Adder blocks (CSA2) and a 6 to 3 Multiplexer (6to3MUX). It has two outputs: 4-bit S[3..0] and a 1-bit C_out (carry out).

VHDL code for a 4-bit Conditional Sum Adder (CSA4):

-- 4-bit Conditional Sum Adder (CSA4)
-- inputs: C_in (carry in), X[3..0], Y[3..0]
-- outputs: S[3..0], C_out (carry out)

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity CSA4 is
    PORT( C_in: in bit;
          X, Y: in bit_vector(3 downto 0);
          S: out bit_vector(3 downto 0);
          C_out: out bit);
end CSA4;


architecture logic of CSA4 is

    component CSA2 is
        PORT( C_in: in bit;
              X, Y: in bit_vector(1 downto 0);
              S: out bit_vector(1 downto 0);
              C_out: out bit);
    end component;
   
    component MUX6_3 is
        PORT( sel: in bit;
              X, Y: in bit_vector(2 downto 0);
              m: out bit_vector(2 downto 0));
    end component;
   
    constant c: bit :='1';
    signal m_sel: bit;
    signal mx, my: bit_vector(2 downto 0);
    signal st: bit_vector(2 downto 0);
   
   
begin

    csa2_inst0 : CSA2
    PORT MAP(C_in => C_in, X => X(1 downto 0), Y => Y(1 downto 0),
             S => S(1 downto 0), C_out => m_sel);
             
    csa2_inst1 : CSA2
    PORT MAP(C_in => c, X => X(3 downto 2), Y => Y(3 downto 2),
             S => mx(1 downto 0), C_out => mx(2));
             
    csa2_inst2 : CSA2
    PORT MAP(C_in => not c, X => X(3 downto 2), Y => Y(3 downto 2),
             S => my(1 downto 0), C_out => my(2));
             
    mux6_3_inst0 : MUX6_3
    PORT MAP(sel => m_sel, X => mx, Y => my,
             m => st);
             
    S(3 downto 2) <= st(1 downto 0);
    C_out <= st(2);
   
end logic;

6 to 3 Multiplexer

Logic gate for a 6 to 3 Multiplexer:

It uses three inputs: one 1-bit sel (selector), 3-bit X (X0, X1, X2) and 3-bit Y (Y0, Y1, Y2), it also uses a 4to2 multiplexer (MUX4_2), two AND gates and one OR gate. It has a 3-bit output m.

VHDL code for the 6 to 3 Multiplexer:

-- 6 to 3 Multiplexer
-- inputs: 1bit sel, 3bit X, 3bitY
-- outputs: 3bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity MUX6_3 is
    PORT( sel: IN bit; 

          X, Y: IN bit_vector(2 downto 0);
          m: OUT bit_vector(2 downto 0));
end MUX6_3;


architecture logic of MUX6_3 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
              m0 => m(0), m1 => m(1));
             
    m(2) <= (X(2) and sel) or (Y(2) and not sel);
end logic;

2 bit Conditional Sum Adder (CSA2)

Logic gate for a 2-bit Conditional Sum Adder (CSA2):

It uses 3 inputs: 1 bit C_in (carry in), 2 bit X (X0, X1), 2 bit Y (Y0, Y1), as CSA1s it uses three 1-bit full adders (FA), one 4 to 2 multiplexer (4to2MUX) and two outputs: 2 bit S (S0, S1) and 1 bit C_out (carry out).

VHDL code for 2-bit Conditional Sum Adder (CSA2):

-- 2 bit Conditional Sum Adder (CSA2)
-- inputs: X[1..0], Y[1..0], C_in (carry in)
-- outputs: S[1..0], C_out (carry out)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity CSA2 is
    PORT ( C_in: in bit;
           X, Y: in bit_vector(1 downto 0);
           S: out bit_vector(1 downto 0);
           C_out: out bit);
end CSA2;


architecture logic of CSA2 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
    component FA is
        PORT ( C_in, X, Y: in bit;
               S, C_out: out bit);
    end component;
   
    signal m_sel, mX0, mX1, mY0, mY1: bit;
    constant c: bit := '1';
   
   
begin

    fa_inst0 : FA
    PORT MAP( C_in => C_in, X => X(0), Y => Y(0),
              S => S(0), C_out => m_sel);
             
    fa_inst1: FA
    PORT MAP( C_in => c, X => X(1), Y => Y(1),
              S => mX0, C_out => mX1);
             
    fa_inst2: FA
    PORT MAP( C_in => not c, X => X(1), Y => Y(1),
              S => mY0, C_out => mY1);
             
    mux4_2_inst0: MUX4_2
    PORT MAP( sel => m_sel,
              X0 => mX0, X1 => mX1, Y0 => mY0, Y1 => mY1,
              m0 => S(1), m1 => C_out);
                          
end logic;

4 to 2 Multiplexer

Logic gate for a 4to2 Multiplexer:

It uses five inputs: 2-bit X, 2-bit Y and 1-bit sel (selector), two 1 bit outputs: m0 and m1, four AND gates, two OR gates and a NOT gate.

VHDL code for the 4to2 Multiplexer:

-- 4to2 Multiplexer

-- inputs: sel, X0, X1, Y0, Y1

-- outputs: m0, m1

LIBRARY ieee;

USE ieee.std_logic_1164.all; 

entity MUX4_2 is

   PORT( sel: in bit; X0: in bit; X1: in bit; Y0: in bit; Y1: in bit;

         m0: out bit; m1: out bit); 

end MUX4_2; 

architecture logic of MUX4_2 is
begin 

   m0 <= (X0 and sel) or (Y0 and not sel);
   m1 <= (X1 and sel) or (Y1 and not sel);
end logic;

1-bit Full Adder

Logic gate for an 1-bit Full Adder:

It uses three 1-bit inputs: C_in (carry in), X, Y, two 1-bit outputs: S and C_out (carry out), two half adder (HA) blocks and one OR gate.

The VHDL code for the 1-bit Full Adder:

-- 1 bit Full Adder
-- inputs:  C_in, X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity FA is
    PORT( C_in : IN bit; X: IN bit; Y: IN bit;
          S: OUT bit; C_out: OUT bit);
end FA;

architecture logic of FA is

    component ha is
        PORT( X: IN bit; Y: IN bit;
              S: OUT bit; C_out: OUT bit);
    end component;
   
    signal ha2Y: bit;
    signal or2Y: bit;
    signal or2X: bit;
           
begin
    ha_inst0: HA
    PORT MAP(
        X => X, Y => Y,
        S => ha2Y, C_out => or2Y);
       
    ha_inst1: HA
    PORT MAP(
        X => C_in, Y => ha2Y,
        S => S, C_out => or2X);
       
    C_out <= or2X OR or2Y;
   
end logic;

1-bit Half Adder

Here is the logic gate for an 1-bit Half Adder (HA)

It uses two 1-bit inputs: X and Y, two 1-bit outputs: S and C_out (carry out), one XOR gate and one AND gate.

And here is the VHDL equivalent code:

-- 1 bit Half Adder
-- inputs: X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity HA is
   PORT( X: in bit; Y: in bit;
         S: out bit; C_out: out bit);
end HA;

architecture logic of HA is 
begin
    S <= X xor Y;
    C_out <= X and Y;
end logic;