4-bit Conditional Sum Adder (CSA4)

Logic gate for a 4 bit Conditional Sum Adder (CSA4):

It uses three inputs:  one 1-bit C_in (carry in) and two 4-bit summands X[3..0], Y[3..0]. It makes use of three 2-bit Conditional Sum Adder blocks (CSA2) and a 6 to 3 Multiplexer (6to3MUX). It has two outputs: 4-bit S[3..0] and a 1-bit C_out (carry out).

VHDL code for a 4-bit Conditional Sum Adder (CSA4):

-- 4-bit Conditional Sum Adder (CSA4)
-- inputs: C_in (carry in), X[3..0], Y[3..0]
-- outputs: S[3..0], C_out (carry out)

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity CSA4 is
    PORT( C_in: in bit;
          X, Y: in bit_vector(3 downto 0);
          S: out bit_vector(3 downto 0);
          C_out: out bit);
end CSA4;


architecture logic of CSA4 is

    component CSA2 is
        PORT( C_in: in bit;
              X, Y: in bit_vector(1 downto 0);
              S: out bit_vector(1 downto 0);
              C_out: out bit);
    end component;
   
    component MUX6_3 is
        PORT( sel: in bit;
              X, Y: in bit_vector(2 downto 0);
              m: out bit_vector(2 downto 0));
    end component;
   
    constant c: bit :='1';
    signal m_sel: bit;
    signal mx, my: bit_vector(2 downto 0);
    signal st: bit_vector(2 downto 0);
   
   
begin

    csa2_inst0 : CSA2
    PORT MAP(C_in => C_in, X => X(1 downto 0), Y => Y(1 downto 0),
             S => S(1 downto 0), C_out => m_sel);
             
    csa2_inst1 : CSA2
    PORT MAP(C_in => c, X => X(3 downto 2), Y => Y(3 downto 2),
             S => mx(1 downto 0), C_out => mx(2));
             
    csa2_inst2 : CSA2
    PORT MAP(C_in => not c, X => X(3 downto 2), Y => Y(3 downto 2),
             S => my(1 downto 0), C_out => my(2));
             
    mux6_3_inst0 : MUX6_3
    PORT MAP(sel => m_sel, X => mx, Y => my,
             m => st);
             
    S(3 downto 2) <= st(1 downto 0);
    C_out <= st(2);
   
end logic;