8 to 4 Multiplexer

Logic gate for an 8 to 4 Multiplexer (8to4MUX):

It has 3 inputs: 1-bit sel (selector), 4-bit X[3..0] and 4-bit Y[3..0]. It uses two 4to2 Multiplexer blocks (4to2MUX). It has one 4-bit output m[3..0].

VHDL code for the 8to4 Multiplexer:

-- 8 to 4 Multiplexer
-- inputs: 1-bit sel (selector), 4-bit X, 4-bit Y
-- outputs: 4-bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity MUX8_4 is
    PORT( sel: in bit;
          X, Y: in bit_vector(3 downto 0);
          m: out bit_vector(3 downto 0));
end MUX8_4;


architecture logic of MUX8_4 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(0), X1 => X(1), Y0 => Y(0), Y1 => Y(1),
              m0 => m(0), m1 => m(1));
             
    mux4_2_inst1 : MUX4_2
    PORT MAP( sel => sel, X0 => X(2), X1 => X(3), Y0 => Y(2), Y1 => Y(3),
              m0 => m(2), m1 => m(3));        
end logic;