8-bit Conditional Sum Adder (CSA8)

Logic gate for an 8-bit Conditional Sum Adder (CSA8). Here carry_in (C_in) and carry_out (C_out) are used (in the eventuality of a 16-bit extension).

It has three inputs: 1-bit C_in (carry_in - not used in the VHDL code!), 8-bit X[7..0] and 8-bit Y[7..0]. It uses three 4-bit Conditional Sum Adder (CSA4) blocks and one 10 to 5 Multiplexer (10to5MUX) block. It has two outputs: 8-bit S[7..0] and C_out (carry_out - not used in the VHDL code!).

VHDL code for the 8-bit Conditional Sum Adder (CSA8):

-- 8-bit Conditional Sum Adder (CSA8)
-- inputs: X[7..0], Y[7..0]
-- outputs: S[7..0]
-- carry_in and carry_out not used!!! (do not intend to extend on 16-bit!)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity CSA8 is
    PORT (X, Y: in bit_vector(7 downto 0);
          S: out bit_vector(7 downto 0));
end CSA8;

architecture logic of CSA8 is

    component CSA4 is
        PORT( C_in: in bit;
              X, Y: in bit_vector(3 downto 0);
              S: out bit_vector(3 downto 0);
              C_out: out bit);
    end component;
   
    component MUX10_5 is
        PORT( sel: in bit;
              X, Y: in bit_vector(4 downto 0);
              m: out bit_vector(4 downto 0));
    end component;
   
    constant c: bit := '1';
    signal msel: bit;
    signal mx, my: bit_vector(4 downto 0);
   
   
begin
    csa4_inst0 : CSA4
    PORT MAP( C_in => '0', X => X(3 downto 0), Y => Y(3 downto 0),
              S => S(3 downto 0), C_out => msel);
             
    csa4_inst1 : CSA4
    PORT MAP( C_in => c, X => X(7 downto 4), Y => Y(7 downto 4),
              S => mx(3 downto 0), C_out => mx(4));
             
    csa4_inst2 : CSA4
    PORT MAP( C_in => not c, X => X(7 downto 4), Y => Y(7 downto 4),
              S => my(3 downto 0), C_out => my(4));
             
    mux10_5_inst0 : MUX10_5
    PORT MAP( sel => msel, X => mx, Y => my,
              m(3 downto 0) => S(7 downto 4));         
end logic;