2 bit Conditional Sum Adder (CSA2)

Logic gate for a 2-bit Conditional Sum Adder (CSA2):

It uses 3 inputs: 1 bit C_in (carry in), 2 bit X (X0, X1), 2 bit Y (Y0, Y1), as CSA1s it uses three 1-bit full adders (FA), one 4 to 2 multiplexer (4to2MUX) and two outputs: 2 bit S (S0, S1) and 1 bit C_out (carry out).

VHDL code for 2-bit Conditional Sum Adder (CSA2):

-- 2 bit Conditional Sum Adder (CSA2)
-- inputs: X[1..0], Y[1..0], C_in (carry in)
-- outputs: S[1..0], C_out (carry out)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity CSA2 is
    PORT ( C_in: in bit;
           X, Y: in bit_vector(1 downto 0);
           S: out bit_vector(1 downto 0);
           C_out: out bit);
end CSA2;


architecture logic of CSA2 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
    component FA is
        PORT ( C_in, X, Y: in bit;
               S, C_out: out bit);
    end component;
   
    signal m_sel, mX0, mX1, mY0, mY1: bit;
    constant c: bit := '1';
   
   
begin

    fa_inst0 : FA
    PORT MAP( C_in => C_in, X => X(0), Y => Y(0),
              S => S(0), C_out => m_sel);
             
    fa_inst1: FA
    PORT MAP( C_in => c, X => X(1), Y => Y(1),
              S => mX0, C_out => mX1);
             
    fa_inst2: FA
    PORT MAP( C_in => not c, X => X(1), Y => Y(1),
              S => mY0, C_out => mY1);
             
    mux4_2_inst0: MUX4_2
    PORT MAP( sel => m_sel,
              X0 => mX0, X1 => mX1, Y0 => mY0, Y1 => mY1,
              m0 => S(1), m1 => C_out);
                          
end logic;