10 to 5 Multiplexer

Logic gate for a 10 to 5 Multiplexer (10to5MUX):

It has three inputs: 1-bit sel (selector), 5-bit X[4..0] and 5-bit Y[4..0]. It uses a 6 to 3 Multiplexer block (6to3MUX) and a 4 to 2 Multiplexer block (4to2MUX). It has a 5-bit output m[4..0].

VHDL code for the 10 to 5 Multiplexer:

-- 10 to 5 Multiplexer
-- inputs: 1-bit sel (selector), 5-bit X, 5-bit Y
-- outputs: 5-bit m

LIBRARY ieee;
USE ieee.std_logic_1164.all;


entity MUX10_5 is
    PORT( sel: in bit;
          X, Y: in bit_vector(4 downto 0);
          m: out bit_vector(4 downto 0));
end MUX10_5;

architecture logic of MUX10_5 is

    component MUX6_3 is
        PORT( sel: in bit;
              X, Y: in bit_vector(2 downto 0);
              m: out bit_vector(2 downto 0));
    end component;
   
    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
begin

    mux6_3_inst0 : MUX6_3
    PORT MAP( sel => sel, X => X(2 downto 0), Y => Y(2 downto 0),
              m => m(2 downto 0));
             
    mux4_2_inst0 : MUX4_2
    PORT MAP( sel => sel, X0 => X(3), X1 => X(4), Y0 => Y(3), Y1 => Y(4),
              m0 => m(3), m1 => m(4));
             
end logic;