2 bit Conditional Sum Adder (CSA2)

Logic gate for a 2-bit Conditional Sum Adder (CSA2):

It uses 3 inputs: 1 bit C_in (carry in), 2 bit X (X0, X1), 2 bit Y (Y0, Y1), as CSA1s it uses three 1-bit full adders (FA), one 4 to 2 multiplexer (4to2MUX) and two outputs: 2 bit S (S0, S1) and 1 bit C_out (carry out).

VHDL code for 2-bit Conditional Sum Adder (CSA2):

-- 2 bit Conditional Sum Adder (CSA2)
-- inputs: X[1..0], Y[1..0], C_in (carry in)
-- outputs: S[1..0], C_out (carry out)

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity CSA2 is
    PORT ( C_in: in bit;
           X, Y: in bit_vector(1 downto 0);
           S: out bit_vector(1 downto 0);
           C_out: out bit);
end CSA2;


architecture logic of CSA2 is

    component MUX4_2 is
        PORT( sel, X0, X1, Y0, Y1: in bit;
              m0, m1: out bit);
    end component;
   
    component FA is
        PORT ( C_in, X, Y: in bit;
               S, C_out: out bit);
    end component;
   
    signal m_sel, mX0, mX1, mY0, mY1: bit;
    constant c: bit := '1';
   
   
begin

    fa_inst0 : FA
    PORT MAP( C_in => C_in, X => X(0), Y => Y(0),
              S => S(0), C_out => m_sel);
             
    fa_inst1: FA
    PORT MAP( C_in => c, X => X(1), Y => Y(1),
              S => mX0, C_out => mX1);
             
    fa_inst2: FA
    PORT MAP( C_in => not c, X => X(1), Y => Y(1),
              S => mY0, C_out => mY1);
             
    mux4_2_inst0: MUX4_2
    PORT MAP( sel => m_sel,
              X0 => mX0, X1 => mX1, Y0 => mY0, Y1 => mY1,
              m0 => S(1), m1 => C_out);
                          
end logic;

4 to 2 Multiplexer

Logic gate for a 4to2 Multiplexer:

It uses five inputs: 2-bit X, 2-bit Y and 1-bit sel (selector), two 1 bit outputs: m0 and m1, four AND gates, two OR gates and a NOT gate.

VHDL code for the 4to2 Multiplexer:

-- 4to2 Multiplexer

-- inputs: sel, X0, X1, Y0, Y1

-- outputs: m0, m1

LIBRARY ieee;

USE ieee.std_logic_1164.all; 

entity MUX4_2 is

   PORT( sel: in bit; X0: in bit; X1: in bit; Y0: in bit; Y1: in bit;

         m0: out bit; m1: out bit); 

end MUX4_2; 

architecture logic of MUX4_2 is
begin 

   m0 <= (X0 and sel) or (Y0 and not sel);
   m1 <= (X1 and sel) or (Y1 and not sel);
end logic;

1-bit Full Adder

Logic gate for an 1-bit Full Adder:

It uses three 1-bit inputs: C_in (carry in), X, Y, two 1-bit outputs: S and C_out (carry out), two half adder (HA) blocks and one OR gate.

The VHDL code for the 1-bit Full Adder:

-- 1 bit Full Adder
-- inputs:  C_in, X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity FA is
    PORT( C_in : IN bit; X: IN bit; Y: IN bit;
          S: OUT bit; C_out: OUT bit);
end FA;

architecture logic of FA is

    component ha is
        PORT( X: IN bit; Y: IN bit;
              S: OUT bit; C_out: OUT bit);
    end component;
   
    signal ha2Y: bit;
    signal or2Y: bit;
    signal or2X: bit;
           
begin
    ha_inst0: HA
    PORT MAP(
        X => X, Y => Y,
        S => ha2Y, C_out => or2Y);
       
    ha_inst1: HA
    PORT MAP(
        X => C_in, Y => ha2Y,
        S => S, C_out => or2X);
       
    C_out <= or2X OR or2Y;
   
end logic;

1-bit Half Adder

Here is the logic gate for an 1-bit Half Adder (HA)

It uses two 1-bit inputs: X and Y, two 1-bit outputs: S and C_out (carry out), one XOR gate and one AND gate.

And here is the VHDL equivalent code:

-- 1 bit Half Adder
-- inputs: X, Y
-- outputs: S, C_out

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity HA is
   PORT( X: in bit; Y: in bit;
         S: out bit; C_out: out bit);
end HA;

architecture logic of HA is 
begin
    S <= X xor Y;
    C_out <= X and Y;
end logic;